Careers

1st Year Anniversary Of Appex Semiconductors

New Year Party - 2019

Committed to having a high employee engagement within its organization, AppEx Semiconductor has adopted a work culture which offers every employee an opportunity to grow, discover and expand their personal and professional prospects through a seamless transition between their roles at home and office. Apart from annual bonus and hikes, AppEx Semiconductor management has adopted some of the employee-friendly strategies.

Anand Sudhir

General Manager, HR

AppEx is looking for a smart and enterprising leader with expert knowledge in SOC Verification to come and lead SOC Verification projects. You will be responsible for leading and managing a team, client communication and project execution.

This role will include:

1. Technical Management Of SOC Verification Projects Of Complex SOC’s

2. Leading And Managing SOC’s Teams For Appex Semiconductors

3. Customer Interaction And Leadership

4. If you are looking for an opportunity to join one of the best Design Verification teams and also work in a great environment where work is Always Fun and Exciting - come join us - we are looking for people just like you!

8 - 12 Years’ Experience In Design Verification

  • 1. Expert Knowledge In SOC Verification
  • 2. Past Experience Leading And Managing Teams Highly Desired
  • 3. Excellent Communication And Presentation Skills
  • 4. Expert At Verification - Coverage Driven Test Planning, Architecting Environments, Verification Flow
  • 5. Expert In System Verilog
  • 6. Knowledge In At Least One Methodology, OVM, UVM, VMM.
  • 7. Gate level simulation setup and debugging
  • 8. RAL Modelling
  • 9. Ability And Desire To Learn New Methodologies, Languages, Protocols Etc. Is Required
  • 1. Prior Leadership Experience Not Necessary But Is Highly Desired
  • 2. Very Good Knowledge Of Protocols, At Least One Protocol Of SATA, Ethernet, PCIE.

Bangalore, Noida, Chennai, Hyderabad, Coimbatore

AppEx is looking for a smart and enterprising engineers with expert knowledge in IP and Sub system verification. This role will include:

1. Create Verification Plans For Sub systems and IP Blocks

2. Create Testbenches In SystemVerilog With UVM methodology

3. Utilize Advanced Verification Techniques

3-5 Years Experience In Design Verification Engineer

  • 1. Experience With SystemVerilog
  • 2. Experience With The UVM Reuse Methodology
  • 3. Experience With Advanced Verification Techniques Like Constrained Random Generation, Functional Coverage, Assertions And Formal Verifiers
  • 4. Good Problem Solving And Debugging Skills
  • 1. Experience With One Or more simulators from the major EDA suppliers (Cadence, Mentor Or Synopsys)
  • 2. Good Software Skills In Object Oriented Programming (OOP), C, C++, Perl, Tcl, Csh

Bangalore, Noida, Chennai, Hyderabad, Coimbatore

AppEx is looking for a smart and enterprising engineers with expert knowledge in IP and Sub system verification. This role will include:

1. Create Verification Plans for SOCs And IP Blocks

2. Create Testbenches In SystemVerilog With UVM methodology

3. Utilize Advanced Verification Techniques

4. Write Tools And Scripts In Perl And Other Script Languages To Enhance The Verification Process

5-7 Years Experience In Design Verification Engineer

  • 1. Experience With SystemVerilog
  • 2. Experience With The UVM Reuse Methodology
  • 3. Experience With Advanced Verification Techniques Like Constrained Random Generation, Functional Coverage, Assertions And Formal Verifiers
  • 4. Gate level simulation setup and debugging
  • 5. RAL Modelling
  • 6. Good Problem Solving And Debugging Skills
  • 1. Experience With One Or more simulators from the major EDA suppliers (Cadence, Mentor Or Synopsys)
  • 2. Experience With Tools For Regression Management, Configuration Management And Bug Tracking
  • 3. Good Software Skills In Object Oriented Programming (OOP), C, C++, Perl, Tcl, Csh

Bangalore, Noida, Chennai, Hyderabad, Coimbatore

AppEx is looking for a smart and enterprising engineers with expert knowledge DFT. This role will include:

1. Working with stakeholders to architect and implement DFT requirements.

2. JTAG, MBIST and SCAN Insertion to performed

3. Pattern generation and simulation

4. Work on coverage Improvement

3-5 Years Experience In DFT

  • 1. JTAG
  • 2. MBIST
  • 3. SCAN
  • 4. ATPG
  • 5. SIMULATION
  • 1. Coverage improvement techniques
  • 2. Good Software Skills In Object Oriented Programming (OOP), C, C++, Perl, Tcl, Csh

Bangalore, Noida, Chennai, Hyderabad, Coimbatore