Our DFT methodology can provide a complete solution including MBIST, regular scan, AC scan, scan compression, boundary scan (JTAG), power aware test and ATPG to achieve limit tending to a 100% test coverage
"Our DFT methodology can provide a complete solution including MBIST, regular scan, AC scan, scan compression, boundary scan (JTAG), power aware test and ATPG to achieve limit tending to a 100% test coverage"
Our primary focus is to provide silicon with least defects, reduce the cost and time associated with test development and reduce the execution time of performing tests on fabricated chips. We also focus on DFT techniques for digital logic, analog/mixed-signal components.
Implementation Methodologies