"A Good Design leads to the next solution with the least application level issues. We are efficient designers, micro-architects, RTL integrators providing quality results reducing verification cycles for TTM."
With a proven physical design flow, methodologies and dedicated subject matter experts: Appex Semiconductors is the leading RTL design services provider for highly complex designs.
Our RTL Design team has profound knowledge of RTL design, synthesis, static timing analysis, formal verification, PLDRC, clock domain crossing and low power techniques.
- Top-level requirements
- Specifies the top-level goal of the IC with the top-level constraints under which this goal has to be achieved
- Specifies the detailed design in terms of hardware blocks and software components of the IC
- Design creation
- For new blocks, RTL design is created and blocks (IPs) identified to be reused are sourced either in-house or from IP vendor
- RTL analysis
- All the blocks are verified using static analysis tools to detect and fix the issues early.
- Functional verification
- A mix of cycle-based simulation and formal verification is used to ensure that RTL design meets the intended functionality
- Based on timing, power and area constraints, the RTL of all the blocks are synthesized into netlist for targeted technology
- Netlist analysis
- This is done using formal equivalence with RTL, gate-level simulation, power analysis and static timing analysis etc.
- Design For Test (DFT)
- Netlist is post-processed for test coverage requirements and to improve test coverage. There are multiple procedures implemented for Yield improvement and avoiding faults in the production chips.
- Backend phase – Performing all the verifications again on Placement & Routing netlist
- Simulation Friendly RTL
- Timing-Analysis Friendly RTL
- Clock-Domain-Crossing (CDC) Friendly RTL
- Power Friendly RTL
- DFT Friendly RTL